Protection of device edges is an essential aspect of the design of high voltage semiconductor devices such as MOSFETs, IGBTs, MCTs, bipolar transistors, thyristors, and diodes. The edge protection, or edge termination structure, must perform the function of distributing the applied voltage over a wider region on the surface of the device than it occupies within the silicon substrate, hereby ensuring that the electric field at the surface is low enough to prevent arcing outside the silicon substrate or avalanche breakdown within the substrate near its surface.
Various edge termination techniques have been developed, including, for example, field plate (FP), described in F. Conti and M. Conti, “Surface breakdown in silicon planar diodes equipped with field plate,” Solid State Electronics, Vol. 15, pp 93-105, the disclosure of which is incorporated herein by reference. Another edge termination approach is field limiting rings (FLR), described in Kao and Wolley, “High voltage planar p-n junctions,” Proc. IEEE, 1965, Vol. 55, pp. 1409-1414, the disclosure of which is incorporated herein by reference. Further edge termination structures utilized junction termination extension (JTE), described in V. A. K. Temple, “Junction termination extension, a new technique for increasing avalanche breakdown voltage and controlling surface electric field in p-n junction,” IEEE International Electron Devices Meeting Digest, 1977 Abstract 20.4, pp 423-426 and variable lateral doping concentration (VLD), described in R. Stengl et al., “Variation of lateral doping as a field terminator for high-voltage power devices”, IEEE Trans. Electron Devices, 1986, Vol. ED-33, No. 3, pp 426-428, the disclosures of which are incorporated herein by reference.
Typically, a planar diffusion technique is used to produce a P-N junction diode, which yields a cylindrical junction. Because of the curvature at the edge of the junction it produces a greater electric field than an ideal planar junction. As a result, the breakdown voltage of a cylindrical junction diode is substantially lower than that of an ideal planar junction diode. Edge termination techniques are used to reduce the concentration of the electric field in a cylindrical junction diode.
U.S. Pat. No. 6,215,168 B1 to Brush et al., the disclosure of which is incorporated herein by reference, describes a semiconductor die that comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed in the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge termination zone comprising a junction termination extension (JTE) region that includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at the point beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point.
Finding an improved way to reduce the electric field at the junction of the active area and the JTE region of a power semiconductor device, the JTE region having a laterally constant or varying (VLD) dopant density, and thereby increasing its breakdown voltage remains a highly desirable goal.